1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of data input/output lines and configured capable of multi-bit simultaneous read.
2. Description of the Related Art
A semiconductor memory device such as DRAM, SRAM, FeRAM and flash EEPROM comprises a plurality of memory cells arranged at intersections of word lines and bit lines. The bit line connected to the selected memory cell is connected indirectly via a gate circuit, a data latch, a sense amp, or a data buffer to a data input/output (I/O) line for use in data input/output. Selection of a word line and a bit line by decoders allows data to be read out of the memory cell onto the bit line and read out onto the corresponding data input/output line, thereby performing data read.
There is known a semiconductor memory device comprising a plurality of, for example, eight data input/output lines formed therein and sense circuits individually provided for respective data input/output lines for multi-bit simultaneous read (see JP-A 2003-168287, paragraphs 0023-0048, FIG. 1, for example). To the eight data input/output lines, eight bit lines simultaneously selected are connected via gate circuits and so forth and eight individual sense circuits operate originally for 8-bit simultaneous read.
An arrangement of a plurality of similarly configured memory cell arrays and connections of bit lines of the memory cell arrays to eight data input/output lines provided in each memory cell array can increase the number of simultaneously readable bits to 16, 24, 32 and so on. Cyclic, sequential activation of the plurality of memory cell arrays, or execution of so-called interleaved accesses can reduce the read cycle time even if the simultaneously readable data consists of 8 bits.
Such the semiconductor memory device capable of multi-bit simultaneous read has a problem associated with a wiring capacitance that is increased as the data input/output lines are elongated for wiring. In addition, an increase in integration density increases the junction capacitance. Therefore, the increase in integration density tends to increase the read time per one bit.